1. Technical Field
The present invention relates generally to a semiconductor memory apparatus, and more particularly, to a non-volatile memory apparatus and a verification method.
2. Related Art
A non-volatile memory apparatus such as a flash memory apparatus is being widely used for a computer, a memory card and the like. In addition, with broadening uses of a portable device such as a smartphone and a digital camera, the non-volatile memory apparatus is replacing a hard disk.
FIG. 1 is a configuration diagram of a known non-volatile memory apparatus.
As illustrated in FIG. 1, a non-volatile memory apparatus 10 includes a memory cell array 110, a page buffer unit 120, a Y decoder 130, an X decoder 140, a power supply 150, and a controller 160 for controlling operations of the non-volatile memory apparatus 10.
In the memory cell array 110, a plurality of memory cells storing data are electrically connected between word lines WL for selecting and activating memory cells and bit lines BL for inputting/outputting data of memory cells.
The page buffer unit 120 includes a plurality of page buffers electrically connected to the memory cell array 110 through the bit lines BL. Also, the page buffer unit 120 provides data to a selected memory cell of the memory cell array 110 in a program operation, or reads data from the selected memory cell of the memory cell array 110 in a read operation.
The Y decoder 130 provides data input/output paths to the page buffers of the page buffer unit 120 under the control of the controller 160, and the X decoder 140 selects the word lines WL of the memory cell array 110 under the control of the controller 160.
The power supply 150 generates an operation voltage according to an operation mode (program, erase and read modes) under the control of the controller 160, and supplies the generated operation voltage to the word lines WL or the page buffer unit 120 through the X decoder 140.
In the non-volatile memory apparatus, a program operation is generally performed using an incremental step pulse program (ISPP) scheme.
FIG. 2 is a diagram explaining a program method in the known non-volatile memory apparatus.
A program pulse Vpgm1 of a first step is applied to program selected memory cells. A verification voltage PVB is applied to the selected memory cells to verify whether a threshold voltage Vth of the memory cell become higher than the verification voltage PVB.
A program pulse Vpgm2 of a second step is applied to program memory cells which have not passed the program verification. At this time, the program pulse Vpgm2 is applied to all the memory cell coupled to a word line the program pulse Vpgm2 is applied, and thus the program pulse Vpgm2 is also applied to the memory cell which have passed the program verification. Nevertheless, memory cells which have passed the program verification are not programmed by making the memory cells a program inhibition state.
Similarly, after the program pulse Vpgm2 of the second step is applied to program the memory cells, the threshold voltages Vth of the memory cells are compared with the verification voltage PVB, i.e., the memory cells are verified as to whether a threshold voltage Vth of the memory cell become higher than the verification voltage PVB. Further, the program and verification operation is performed while gradually increasing (Vpgm3, Vpgm4, . . . ) the program pulse until all the memory cells are programmed.
If all memory cells to be programmed have the same program speed, the threshold voltages of the programmed memory cells have substantially the same distribution as that before the memory cells are programmed.
However, it is not possible for the memory cells to have the same program speed due to various reasons occurring in the process of fabricating the memory apparatus, a change in external conditions with the use of the memory apparatus, and the like. Therefore, in the program operation, there exist cells (high speed program cells) programmed at a high speed and cells (low speed program cells) programmed at a low speed. Further, the program operation may be completed when all the memory cells including the low speed program cells are programmed.
Although a difference exists in the program speed as described above, the program operation is performed by the same program pulse at the same time, and thus a threshold voltage distribution of a programmed memory cell has a certain width.
FIG. 3 is a diagram explaining threshold voltage distribution of cells in the known non-volatile memory apparatus.
It is assumed that memory cells with low threshold voltage levels CL0 are programmed and the threshold voltages of the memory cells move to high threshold voltage levels CL1.
The memory cells with the low threshold voltage levels CL0 include high speed program cells FC and low speed program cells SC, and the increases of the threshold voltages of the high speed program cells FC by a program pulse is larger than that of low speed program cells SC.
Further, since the program operation is completed when threshold voltages of all cells become higher than a verification voltage PVB, the threshold voltage distribution of the programmed memory cell has a certain width.
If the step voltage of the ISPP decreases, the width of the threshold voltage distribution may decrease. However, in this case, a program operation time may increase.
The width of the threshold voltage distribution of memory cells in the non-volatile memory apparatus is an important factor for determining a read margin. In this regard, various attempts are being made to reduce the width of the threshold voltage distribution.